Parametric Timing Failures and Defect-based Testing in Nanotechnology CMOS Digital ICs

Parametric failures have been with us since the beginning of CMOS technology, but their significance is now more serious and growing. We refer to ac parametric timing failures that fall into two classes: (1) intrinsic ICs (free of defects), and (2) extrinsic ICs (presence of defects. The succession of 180 nm, 130 nm, and 90 nm CMOS IC technologies show an increasing lack of manufacturing control of circuit parameter variance. The spread of statistical parameters from their target, such as Leff , Vt , metal line width and spacing, FMAX , VDD(min), etc., presents subtle failures or degradations called parametric (timing) failures. Our presentation will show fab statistics of these parameters and how they cause peculiar failures. The properties of intrinsic and extrinsic ICs are summarized in a defect-based test (DBT) analysis showing what detection approaches are affected and those that aren’t.